1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, specifically to a structure and a manufacturing method of a high voltage MOS transistor.
2. Description of the Related Art
FIG. 5 is a cross-sectional view showing a structure of an N-channel high voltage MOS transistor according to a prior art. A gate electrode 52 is formed on a P-type silicon substrate 50 through a gate insulation film 51. A sidewall spacer 53 made of an insulation film is formed on each sidewall of the gate electrode 52. A source layer 54 composed of an N−-type source layer 54a and an N+-type source layer 54b and a drain layer 55 composed of an N−-type drain layer 55a and an N+-type drain layer 55b are formed.
The high voltage MOS transistor attains a high drain withstand voltage by placing the N−-type drain layer 55a adjacent the gate electrode 52 and placing the N+-type drain layer 55b away from the gate electrode 52 to relax a drain electric field.
Further description on such a high voltage MOS transistor is found, for example, in Japanese Patent Publication No. H05-218070.
In order to enhance the drain withstand voltage, it is necessary that a dose of implanted ions to form the N−-type drain layer 55a is decreased to reduce an impurity concentration in the N−-type drain layer 55a. When the impurity concentration in the N−-type drain layer 55a is simply reduced, however, the impurity concentration may become too low in an uppermost surface of the N−-type drain layer 55a. 
When a channel current flows through the high voltage MOS transistor having the N−-type drain layer 55a of the excessively reduced impurity concentration, there arises a problem that a saturation current Idsat of the high voltage MOS transistor substantially varies with injection of hot carriers into the gate insulation film 51 induced by the channel current. If the impurity concentration is not reduced, on the other hand, there is a problem that the operational withstand voltage (a drain withstand voltage when the MOS transistor is turned on) is low.
FIG. 4B shows characteristics of source-drain current Ids before and after the injection of the hot carriers. The substantial variation in the saturation current Idsat of the MOS transistor is due to a change in resistance of the uppermost surface of the N−-type drain layer 55a caused by electric charge of the hot carriers trapped in the gate insulation film 51.